LVCMOS 1.2 is the default I/O selection for these devices.
IGLOO, IGLOO PLUS, and ProASIC3L LVCMOS 1.2 V I/Osġ.2 volt LVCMOS I/O technology is the lowest V CCI standard available and is now available for ProASIC3L, 1.2 volt IGLOO, and 1.2 volt IGLOO PLUS devices. If you are using Flash*Freeze Management IP for the Flash*Freeze type 1, please read Known Issue number 75290.įor more information please see the Libero online help and the Flash*Freeze and Low-Power Modes Technology in IGLOO and ProASIC3L Devices section of the handbook. Actel recommends that you manually instantiate the INBUF_FF macro when using Flash*Freeze type 1. You can generate and instantiate the Flash*Freeze management IP from the Libero IDE Catalog, or, manually instantiate the INBUF_FF macro. New netlists must have the INBUF_FF macro instantiated in the design such that the Flash*Freeze port drives the macro. When using a Designer Block in a Flash*Freeze design, the Flash*Freeze macro, either Type 1 or Type 2, must be inside of the Designer Block. Note: Using v8.3, you can instantiate only one Designer Block in the design. For designs using Flash*Freeze Type1, users must regenerate the programming file using v8.3. You must recompile the design to have the status report available. When converting a design, the status report is no longer available from the menu. The ULSICC macro is used in type 2 to control the entry into Flash*Freeze mode.Įxisting designs (ADB) utilizing Flash*Freeze will be converted automatically when opened with v8.3. The INBUF_FF macro is driven by the design Flash*Freeze port in both type 1 and 2. This block will include an INBUF_FF macro and the optional Flash*Freeze management IP, which includes the ULSICC macro.
Flash*Freeze type selection and management IP can be generated by the Libero IDE core generator and instantiated as a single block in the your design. Libero IDE v8.3 includes a new, convenient, and intuitive design flow for configuring and integrating Flash*Freeze into an FPGA design. This IP also provides the option to perform housekeeping prior to entering Flash*Freeze mode. A new Flash*Freeze management IP offers a robust RTL block that ensures clean clock gating of all system clocks before entering and upon exiting Flash*Freeze mode. This feature enables seamless continuation of data processing before and after Flash*Freeze, without the need to reload or reinitialize the FPGA system. One of the key benefits of Actel's Flash*Freeze mode is the ability to preserve the state of all internal registers, SRAM content, and I/Os (IGLOO PLUS only). Improved Flash*Freeze Flow for IGLOO, IGLOO PLUS, and ProASIC3L For more information regarding these kits or the P1AFS devices, please contact Mike Brogley ( 650.318.4982). The P1AFS devices support reference designs and development kits developed in partnership with Pigeon Point Systems. ** This release also adds support for P1AFS600 and P1AFS1500 devices. For more information regarding the AMC reference design or the U1AFS devices, please contact Mike Brogley ( 650.318.4982). * The U1AFS devices support the Advanced Mezzanine Card (AMC) reference design starter kit, developed in partnership with MicroBlade, Inc.